Charged splitting method using charge transfer device

ABSTRACT

A charge-splitting device and method include a plurality of charge cells coupled to receive a charge in response to being simultaneously clocked into a charge receiving state by an applied clock signal. The received charge is split into predetermined charge portions among the plurality of charge cells in proportions dependent upon the total number of cells, their relative capacitance and the magnitude and timing of the applied clock signal. The charge portions are again split and selectively summed to obtain highly accurate charge splitting ratios.

This is a continuation of application Ser. No. 678,277, filed Apr. 19,1976, now abandoned.

BACKGROUND AND SUMMARY

Shift registers constructed by serially coupling a plurality of chargecells in cascade to form an array are known in the art. Charge istypically transferred from cell to cell in the array in response toclock signals applied to cells of the array.

A received charge can be split among several cells by coupling aplurality of cells to receive the charge and simultaneously clockingselected cells into a charge receiving state.

With such an approach, the splitting ratio is influenced by the cellgate areas. If charge is to be split into two halves, for example, thecharge receiving cells should have identical gate areas. Splittinginaccuracy results if the areas are mismatched. The split charges can beexpressed as follows:

Charge in cell A = pQ =(Q/2)(1 - ε)

Charge in cell B = rQ = (Q/2)(1 + ε),

where ε represents a splitting error caused, for example, by layout orprocessing.

An improved charge splitting device made in accordance with theinvention brings a quantity of charge Q into a splitting cell and splitsthe charge Q into two charge portions pQ and rQ, p and Q being splittingcoefficients where p = 1/2(1 - ε) and r = 1/2(1 + ε ), ε being the errorin charge splitting. The charge portion rQ is stored and the chargeportion pQ is again divided by splitting cell into charge portions p² Qand prQ. The charge portion prQ is equal to (Q/4)(1 - ε²). The chargeportions p² Q and r² Q are summed to produce the quantity (Q/2)(1 + ε²).The charge portions (Q/4)(1 - ε²) and (Q/2)(1 + ε²) are more highlyaccurate representations of Q/4 and Q/2 than representations heretoforeavailable by devices having an ε < 1.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a drawing of a cross section of a conventional Charge CoupledDevice shift register having a linear row of charge-coupled cells.

FIG. 2 is a diagrammatic top view of the charge-coupled device shiftregister of FIG. 1.

FIG. 3 is a diagrammatic top view of a charge-branching cell incombination with two shift registers.

FIG. 4 is a diagrammatic top view of a charge-summing cell incombination with two shift registers.

FIG. 5 is a timing diagram of clock pulse signals φ₁ φ₂.

FIG. 6 is a diagrammatic top view of a charge-splitting cell incombination with two shift registers.

FIG. 7 is a diagrammatic top view of an improved charge splitting cellmade in accordance with the invention.

FIG. 8 is a timing diagram illustrating appropriate clock signals foruse with the embodiment depicted in FIG. 7.

FIG. 9 is a digital to analog converter utilizing charge splitting cellsconstructed as shown in FIG. 7.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIGS. 1 and 2, a conventional Charge Coupled Device (CCDhereinafter) shift register is shown. The register depicted is, forexample, a two-phase device having directionality of charge transfer asdescribed for example by J. E. Carnes and W. F. Kosonocky in the Apr.1974 issue of Solid State Technology at pages 67-77 comprising aplurality of charge-coupled cells 12, 14 and 16 operated by a two-phaseclock producing clock pulse signal φ₁ and φ₂. The CCD shift register istypically constructed of a silicon substrate 2 doped with a p-typeimpurity. The silicon substrate is covered by a first layer 4 of S_(i)O₂. On top of the S_(i) O₂ layer are deposited first gate electrodes 6of, for example, polysilicon, and second gate electrodes 8 of, forexample, aluminum, isolated from each other by a second layer 10 ofS_(i) O₂. The second gate electrodes overlap the gaps between the firstgate electrodes. Adjacent first and second electrodes are interconnectedas shown and the interconnections are alternately coupled to receiveclock phase signals φ₁ and φ₂. FIG. 2 illustrates charge transfer cells12, 14 and 16 formed thereby.

Referring to FIG. 3, a diagrammatic top view of a charge-branching cellin combination with two CCD shift registers is shown. Conventional CCDcells 18, 20, 22 and 24 are coupled in cascade in a first linear arraysimilar to known CCD shift registers. The charge-branching cellcomprises cells 20, 22 and 26. Conventional CCD cells 26, 28 and 30 arecoupled in cascade in a second linear array similar to known CCD shiftregisters. Cell 20, however, is coupled to two adjacent cells 22 and 26,cell 22 being in the first array and cell 26 being in the second array.Gate electrodes of cells 18, 20, 24, 28 and 30 are connected to receiveclock pulses φ₁ and φ₂ as in the conventional shift registersillustrated in FIGS. 1 and 2. Cells 22 and 26 have their first andsecond gate electrodes coupled to receive one of two conditional clockpulses. Aφ₁ and Aφ₁ by means of logic 32 and 34, respectively. Aφ₁ is,for example, representative of a logic AND function of the logicvariable A with the phase signal φ.sub. 1. Similarly, Aφ₁ is, forexample, representative of a logic AND function of the logic variable Awith the phase signal φ₁. Copending U.S. patent applications entitled"Charge Coupled Analog to Digital Converter" and Ser. No. 677,944, nowabandoned, and "Charge Coupled Digital to Analog Converter" Ser. No.677,955, now allowed by Thomas Hornak describe suitable logic and saidpatent applications are hereby fully incorporated by reference. For A =logic zero, the conditional clock phase signal Aφ₁ is zero and no clockphase φ₁ pulses are applied to the gate electrodes of cell 22. Since A =logic zero, A = logic one and cell 26 does receive clock phase signalφ₁. The charge residing in cell 20 will therefore be clocked into cell26. No charge will enter cell 22 as long as its first and second gatesare kept at zero voltage. Further clock pulses φ₁ and φ₂ propagatecharge from cell 26 down the array formed by cells 28 and 30.

For A = logic one and A = logic zero, cell 26 has a zero gate voltageand will not receive any charge from cell 20. The gates of cell 22 will,however, be clocked positively by clock pulses φ₁ and cell 22 willreceive charge from cell 20. Charge 36 applied to the left of the firstlinear array in FIG. 3 is selectively branched to the second lineararray or to the first linear array by application of the logic variablesA and A.

The charge-branching cell comprising cells 20, 22 and 26 therebyprovides selective branching of charge. Although branching to only twoarrays has been described, extension to a larger plurality of branchingis possible.

Referring to FIG. 4, a diagrammatic top view of a charge-summing cell isshown. CCD cells 38, 40 and 42 are coupled in cascade in a first lineararray similar to that of a conventional CCD shift register. Similarly,CCD cells 44, 46, 48 and 50 are coupled in cascade and form a secondarray. Cell 46 is coupled to receive charge from cell 42 in the firstarray and from cell 44 in the second array. Referring to FIG. 5, timingdiagrams for clock pulses φ₁ and φ₂ are shown which can be used for thedevices illustrated in FIGS. 1 through 4. With reference to FIG. 4,assume that at time t₃ indicated in FIG. 5 cells 42 and 44 are eachholding charge and that the gate electrodes of cell 46 are at zerovolts. At time t₄ the three gate electrodes of cell 46 are drivenpositive by clock pulse signal φ₁, with cell 46 still not containingcharge. Between time t₄ and t₅ clock pulse signal φ₂ goes to zero voltswhile clock pulse signal φ₁ remains high. The charges from cells 42 and44 are both transferred into cell 46 and thereby summed in cell 46. Thesummed charge is then clocked into cell 48 when clock signal φ₁ goes tozero volts between times t₆ and t₇ shown in FIG. 5. Although acharge-summing cell is described for summing charge from two sources,extension to larger pluralities is within the scope of the invention.

Referring to FIG. 6, a charge-splitting cell is shown in combinationwith two CCD shift registers. The charge-splitting cell comprises CCDcells 58, 60 and 64. A first CCD shift register comprises cells 52, 54,56 and 68 are coupled in cascade, a second shift register comprisescells 60 and 62, coupled in cascade, and a third shift registercomprises cells 64 and 66. Cell 58 receives charge from cell 56. Thecharge residing in cell 58 at time t₁ indicated in FIG. 5 is transferredto cells 60 and 64 between times t₂ and t₃ in response to cells 60 and64 being simultaneously clocked into a charge receiving state by clockpulse signal φ₂. The distribution of charge between cells 60 and 64 isproportional among other things to the gate area ratios of cells 60 and64. If, for example, cells 60 and 64 are substantially identical, thecharge will be equally split between cells 60 and 64.

Different splitting ratios can be achieved by coupling a greaterplurality of cells to cell 58, for example, three identical cellsprovide a splitting ratio of 1/3. Variations can be achieved by varyingcell gate area size in combination with varying the plurality and alsoby cascading charge-splitting cells as described in referenced and fullyincorporated copending applications entitled "Charge Coupled Analog toDigital Converter" and "Charge Coupled Digital to Analog Converter" byThomas Hornak.

Referring to FIG. 7, an improved charge splitting device is shown. Acharge Q to be split is applied to cell 70. The charge Q is transferredto cell 73 and from there split into cells 74 and 78 as two portions,the first portion being pQ, p equal to a quantity 1/2(1 - ε), and thesecond portion being rQ, r equal to a quantity 1/2(1 + ε), and ε beingrepresentative of proportional splitting error due to masking orprocessing errors and the like. The charge portion pQ is transferredfrom cell 74 to cell 80 and the charge portion rQ is transferred fromcell 78 to cell 73 and split into cells 74 and 78 as charge portions r²Q and prQ, respectively; the charge portion pQ is recalled from cell 80and split into a second charge portion prQ and a charge portion p² Q bycells 73, 74, 78, and the charge portions p² Q and r² Q summed in cell82 to produce the charge portion (Q/2)(1 + ε²) as described more fullybelow.

Referring to the timing diagram shown in FIG. 8 and the diagram of thepreferred embodiment depicted in FIG. 7, at time t₁ the charge Q isunderneath gate φ₁.

At t₂ gate φ₃ is ready to accept charge Q but charge Q is still confinedunder gate φ₁.

At t₃ charge Q is transferred from underneath gate φ₁ to underneath gateφ₃.

At t₄ gates φ₅ and φ₉ are ready to accept charge but charge Q is stillconfined under gate φ₃.

At t₅ a charge portion pQ equal to (Q/2)(1 - ε) is transferred from gateφ₃ of cell 73 to gate φ₅ of cell 74 and a charge portion rQ equal to(Q/2(1 + ε) is transferred from gate φ₃ of cell 73 to gate φ₉ of cell78.

At t₆ gate φ₇ of cell 80 is ready to accept charge from gate φ₅ of cell74 and gate φ₃ of cell 73 is ready to accept charge from gate φ₉ of cell78.

At t₇ charge portion pQ is transferred from cell 74 to cell 80 andcharge portion rQ is transferred from cell 78 to cell 73.

At t₈ gate φ₅ of cell 74 and gate φ₉ of cell 78 are ready to acceptcharge from gate φ₃ of cell 73 but charge portions pQ and rQ are stillunderneath gates φ₇ and φ₃.

At t₉ charge portion rQ is split into charge portions r² Q underneathgate φ₉ of cell 78 and the first charge portion prQ underneath gate φ₅of cell 74.

At t₁₀ gate φ₁₃ of cell 84 and gate φ₁₁ of cell 82 are ready to acceptthe first charge portion prQ from gate φ₅ of cell 74 and charge portionr² Q from gate φ₉ of cell 78, respectively. The first charge portion prQis stored underneath gate φ₅, R² Q is stored underneath gate φ₉ and pQis stored underneath gate φ₇.

At t₁₁ the first portion prQ equal to (Q/4)(1 - ε²) is transferred fromgate φ₅ of cell 74 to gate φ₁₃ of cell 84 and made available as a firstoutput 90. Charge portion r² Q is transferred from gate φ₉ of cell 78 togate φ₁₁ of cell 82. Charge portion pQ is still stored under φ₇.

At t₁₂ gate φ₅ of cell 74 is ready to accept charge portion pQ from gateφ₇ of cell 80 and the first charge portion prQ and charge portion ² Qare still stored under gates φ₁₃ and φ₁₁.

At t₁₃ charge portion pQ is transferred from under gate φ₇ of cell 80 tounder gate φ₅ of cell 74.

At t₁₄ gate φ₃ of cell 73 is ready to accept charge from gate φ₅ of cell74.

At t₁₅ charge portion pQ is transferred from gate φ₅ of cell 74 to gateφ₃ of cell 73.

At t₁₆ gates φ₅ of cell 74 and φ₉ of cell 78 are ready to accept chargefrom gate φ₃ of cell 73.

At t₁₇ charge portion pQ is split into charge portions p² Q and a secondprQ, p² Q being underneath gate φ₅ of cell 74, the second prQ underneathgate φ₉ of cell 78. The first charge portion prQ is still stored undergate φ₁₃ and charge portion r² Q is still stored under gate φ₁₁ (seet₁₁).

At t₁₈ gate φ₁₅ of cell 86 is ready to accept prQ from gate φ₉ of cell78 and gate φ₃ of cell 73 is ready to accept p² Q from gate φ₅ of cell74.

At t₁₉ the second charge portion prQ equal to (Q/4)(1 - ε²) istransferred from gate φ₉ of cell 78 to gate φ₁₅ of cell 86 and isavailable as a second output 92. Charge portion p² Q is transferred fromgate φ₅ of cell 74 to gate φ₃ of cell 73.

At t₂₀ gate φ₉ of cell 78 is ready to accept charge portion p² Q fromgate φ₃ of cell 73.

At t₂₁ charge portion p² Q is transferred from under gate φ₃ of cell 73to under gate φ₉ of cell 78. Gate φ₁ of cell 70 can now accept a newcharge to be split.

At t₂₂ gate φ₁₁ of cell 82 is still storing charge portion r² Q (sincet₁₁) and is now ready to accept in addition charge portion p² Q fromgate φ₉ of cell 78. Gate φ₃ of cell 73 is ready to accept a new chargefrom gate φ₁ of cell 70.

At time t₂₃ charge portion p² Q is transferred from underneath gate φ₉of cell 78 to underneath gate φ₁₁ of cell 82 where it is summed withcharge portion r² Q. The sum equals (Q/4)(1 - ε)² + (Q/4)(1 + ε)² =(Q/2)(1 + ε²) and is available as a third output 94. If ε is less thanone, the charge portions available as outputs 90, 92 and 94 aretherefore more accurate representations of Q/4, Q/4, and Q/2,respectively: (Q/4)(1 - ε²), (Q/4)(1 - ε²) and (Q/2)(1 + ε²), than canbe obtained from a given splitting cell.

Referring to FIG. 9, a digital to analog converter utilizing theembodiment of FIG. 7 in the manner taught by the copending patentapplication titled "Charge Coupled Digital to Analog Converter" byThomas Hornak is shown.

We claim:
 1. A method for splitting charge comprising the stepsof:splitting a quantity of charge Q into a charge portion pQ and acharge portion rQ, p being 1/2 (1-ε), r being 1/2 (1+ε), by a chargesplitting means having a splitting error of ε, ε being a fraction lessthan one; splitting the charge portion pQ into a charge portion p² Q anda charge portion rpQ by said charge splitting means; splitting thecharge portion rQ into a charge portion r² Q and a charge portion prQ bysaid charge splitting means; combining the charge portions p² Q and r²Q; and applying the combined charge portions p² Q and r² Q as an outputrepresentative of one-half the value of charge Q.
 2. A method forsplitting charge comprising the steps of:splitting a quantity of chargeQ into a first plurality of first charge portions; splitting the firstplurality of first charge portions into a second plurality of secondcharge portions; combining a plurality of the second plurality of secondcharge portions to form a combined charge portion; and applying thecombined charge portion as an output.
 3. A method as in claim 2 whereineach of the first plurality of first charge portions is substantiallyequal to the same nominal fractional portion of charge Q.
 4. A method asin claim 2 wherein each of the second plurality of second chargeportions is substantially equal to the same nominal fractional portionof charge Q.
 5. A method as in claim 2 wherein the first and secondcharge portions are each split by a selected splitting cell.
 6. A methodfor splitting charge comprising the steps of:applying a quantity ofcharge Q to a charge splitting cell; splitting the charge Q by means ofsaid charge splitting cell into two charge portions pQ and rQ, p and rbeing splitting coefficients where p = 1/2 (1-ε) and r = 1/2 (1+ ε), εbeing a number representing error of said charge splitting cell;splitting the charge portion pQ by means of said charge splitting cellinto charge portions p² Q and prQ; splitting charge portion rQ by meansof said charge splitting cell into charge portions r² Q and rpQ; andcombining charge portions p² Q and r² Q to form a quantity of chargerepresentative of one-half the quantity of charge Q.
 7. A method as inclaim 6 comprising the additional steps after splitting charge Qof:removing charge portions pQ and rQ from said splitting cell; storingthe charge portion pQ; and storing the charge portion rQ.
 8. A method asin claim 6 wherein the step of splitting the charge portion pQ comprisesthe steps of:applying charge portion pQ to said charge splitting cell;and splitting the charge portion pQ by said charge splitting cell intocharge portions p² Q and prQ.
 9. A method as in claim 8 comprising theadditional steps after splitting charge portion pQ of:removing thecharge portions p² Q and prQ from said splitting cell; and storing thecharge portion p² Q.
 10. A method as in claim 9 wherein the step ofsplitting the charge portion rQ comprises the steps of:applying chargeportion rQ to said charge splitting cell; and splitting the chargeportion rQ by said charge splitting cell into charge portions r² Q andrpQ.
 11. A method as in claim 10 comprising the additional steps aftersplitting charge portion rQ of:removing the charge portions r² Q and rpQfrom said charge splitting cell; and storing the charge portion r² Q.12. A method as in claim 11 wherein the step of combining chargeportions p² Q and r² Q comprises the steps of:applying the chargeportions p² Q and r² Q to a charge summing cell; and combining thecharge portions p² Q and r² Q in the charge summing cell.